Advanced interconnects drive intelligent vision applications: Part 1

The EyeQ2 uses two types of proprietary vector processors: VCE (Vision Computing Engine) and VMP (Vector Microcode Processor). VCE DSPs have a fixed logic architecture to address image preprocessing and search operations, including object classification, object tracking, disparity identification (for applications using stereo images), and filtering for vision analysis.

The VMP engines provide further image and object processing using a high-bandwidth architecture utilizing parallel vector, scalar, and look-up table units. Again, Sonics' generation of the RTL (register transfer level) (and SystemC) for the instantiation of the fabric for enabling the requisite data flows efficiently is vital in meeting schedules for IP integration and verification to achieve system requirements.

Additionally, the two FS2 MIPS 34Kfs, MobilEye VCE/VMP processors, the DMA, and peripheral cores are connected by the Sonics Multi-Service Exchange (SMX^tm) fabric, which enables the efficient functioning of these cores. This can be seen in more detail below.

The Sonics 128 bit 166 MHz SMX (OCP) interconnect services the heavy duty traffic between the SoC components. An additional low-bandwidth 32-bit bus connects low-bandwidth peripherals and the VCE/VMP DMAs configuration register via one of SMX ports.

The EyeQ2 architecture was designed for intensive parallel processing to meet the challenges of vehicle vision applications. EyeQ2 silicon systems available by mid-2007 will be capable of concurrent detection of vehicles, motorcycles, pedestrians, traffic lights, signs, etc.

Page 3: SMX and socket-based SoC design
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